Red Hat Enterprise Linux 10 x86–64-v3 feature

Advancing Performance and Compatibility with x86–64-v3 in Red Hat Enterprise Linux 10

Introduction to x86–64-v3 in RHEL 10

In Red Hat Enterprise Linux (RHEL) 9, Red Hat upgraded the instruction set architecture (ISA) baseline to the x86–64-v2 microarchitecture level. For RHEL 10, Red Hat is exploring an advancement to the x86–64-v3 level, potentially bringing significant performance benefits to various applications, particularly in data science and numerical computing domains.

New CPU Capabilities in x86–64-v3

x86–64-v3 offers substantial improvements over its predecessor:

• Enhanced vector register width in AVX and AVX2 instruction sets from 128 bits to 256 bits, adding new vector operations.
• Support for the fused multiply-add (FMA) instruction, enabling more precise and efficient computations.
• VEX encoding to improve instruction variants and reduce code redundancy, enhancing code density and reducing instruction cache pressure.
• Additional bit manipulation operations for scalar registers, aiding in efficient data processing.

Compatibility Impact